Reducing quantization error in low-energy FIR filter accelerators

Abstract

Computational energy versus computational precision represents a critical implementation-level tradeoff facing embedded DSP systems. Focusing on multiply-accumulate (MAC) hardware, which is used extensively in DSP implementations (e.g., FIR filtering), this paper proposes an approach that exploits floating-point representation of multipliers to enable optimization of their quantization error. The approach introduces a parameter α for coefficient scaling, and optimizes α to minimize the output error. Applied to FIR filters with coefficient representation of 6 bits, the approach reduces the quantization error by 37×, compared to traditional, linear-quantized fixed-point coefficient representation and by 28×, compared to unoptimized floating-point coefficient representation. Further, the energy and hardware gate-count of a MAC unit is reduced by 1.4× and 1.2×, respectively, compared to an implementation based on fixed-point representation.