Convergence-optimized variable node structure for stochastic LDPC decoder

Qichen Zhang; Yun Chen; Di Wu; Xiaoyang Zeng; Yeong-Luh Ueng

ICASSP 2016accepted0 citations

Convergence-optimized variable node structure for stochastic LDPC decoder

Qichen Zhang, Yun Chen, Di Wu, Xiaoyang Zeng, Yeong-Luh Ueng

Abstract

By using stochastic computation, a fully-parallel low-density parity-check (LDPC) decoder can be implemented using a lower wire complexity. In order to enhance the decoder performance, probability tracers, such as up/down counters, are added at each edge between variable nodes and check nodes, as described in previous literature. However, this causes a large decoding latency and a high number of decoding failures. In this paper, a convergence-optimized structure for variable nodes is proposed that is able to overcome these issues. As a result, the throughput for the proposed decoder is 20.5Gb/s, which is 101% higher than the original counter-based decoder presented in the previous literature.

BibTeX

@inproceedings{icassp2016_convergenceoptim,
  title = {Convergence-optimized variable node structure for stochastic LDPC decoder},
  author = {Qichen Zhang and Yun Chen and Di Wu and Xiaoyang Zeng and Yeong-Luh Ueng},
  booktitle = {ICASSP 2016},
  year = {2016}
}