Hardware-oriented Memory-limited Online Fastica Algorithm and Hardware Architecture for Signal Separation
Lan-Da Van, Tsung-Che Lu, Tzyy-Ping Jung, Jo-Fu Wang
Abstract
This paper presents a hardware-oriented memory-limited online FastICA algorithm and its hardware architecture and implementation for eight-channel electroencephalogram (EEG) signal separation. The online algorithm integrates the data overlapping, garbage detection, channel permutation, and momentum-controlled weight update schemes to stabilize the order of the decomposed source signals across time. This study also realizes the algorithm into a hardware architecture and implementation with a core area of 1.469x1.469 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in a TSMC 90 nm process. The resulting power dissipation for eight-channel EEG signal separation is 65 mW@100 MHz at 1V.
BibTeX
@inproceedings{icassp2019_hardwareoriented,
title = {Hardware-oriented Memory-limited Online Fastica Algorithm and Hardware Architecture for Signal Separation},
author = {Lan-Da Van and Tsung-Che Lu and Tzyy-Ping Jung and Jo-Fu Wang},
booktitle = {ICASSP 2019},
year = {2019}
}