Development and Evaluation of Japanese Text-to-speech Middleware for 32-Bit Microcontrollers

Nobuyuki Nishizawa; Tomohiro Obara; Gen Hattori

ICASSP 2019accepted0 citations

Development and Evaluation of Japanese Text-to-speech Middleware for 32-Bit Microcontrollers

Nobuyuki Nishizawa, Tomohiro Obara, Gen Hattori

Abstract

Japanese text-to-speech (TTS) middleware for 32-bit microcontrollers (MCUs) such as Arm Cortex-M4 has been developed. Our TTS middleware is based on HMM-based speech synthesis techniques and includes an analyzer to generate pronunciation from texts that consist of Kanji (ideographic) and Kana (syllabary) characters. The middleware has been highly optimized for MCUs with the succinct data structure for data compression, fixed-point arithmetic for fast processing and pipelined processing to reduce both the required RAM size and response time. In this study, it is demonstrated that a real-time TTS system implemented on a 14-pin DIP-size MCU board that consist mainly of an MCU and external serial NOR flash can synthesize 32 kHz-sampled speech sounds with quality comparable to that of the conventional implementation of the HMM-based speech synthesis. The peak current of the MCU board at that condition is approximately 15 mA.

BibTeX

@inproceedings{icassp2019_developmentandev,
  title = {Development and Evaluation of Japanese Text-to-speech Middleware for 32-Bit Microcontrollers},
  author = {Nobuyuki Nishizawa and Tomohiro Obara and Gen Hattori},
  booktitle = {ICASSP 2019},
  year = {2019}
}