Digitally Annealed Solution for the Vertex Cover Problem with Application in Cyber Security

Abstract

Cyber attacks on the power systems can mislead the control center to produce incorrect state and topology estimate. State and topology attacks can have harmful impacts on the operation of a power system. The problem of placing secure phasor measurement units (PMUs) to detect these attacks has been studied in the literature. Specifically, it has been shown that placing secure PMUs to disable undetectable state and topology attacks can enhance the security of the system against cyber attacks. Placing secure PMUs is indeed the minimum vertex cover problem. Since the cost of deploying PMUs is high, it is important to place the secure PMUs efficiently in order to maximize the ability of detecting cyber attacks while reducing the costs. In this paper, we use Digital Annealer to solve the vertex cover problem. Digital Annealer is a hardware architecture for solving combinatorial optimization problems. We have performed numerous numerical experiments and noticed that our approach has an enhanced level of optimality compared to other well-known alternatives in the literature.