Design-time improvement using a functional approach to specify GraphSLAM with deterministic performance on an FPGA

Robin Appel; Hendrik Folmer; Jan Kuper; Rinse Wester; Jan Broenink

IROS 2017poster2 citations

Design-time improvement using a functional approach to specify GraphSLAM with deterministic performance on an FPGA

Robin Appel, Hendrik Folmer, Jan Kuper, Rinse Wester, Jan Broenink

Abstract

SLAM is a fundamental problem in robotics that can be solved by a set of algorithms that are known to have large computational complexity. GraphSLAM contains a rapidly growing system of equations which are often solved by sparse evaluation techniques. This paper proposes a technique to evaluate sparse equations on an FPGA by restricting the maximum amount of items in the system. The implementation is done using CλaSH which allows a transformation from mathematical descriptions to a hardware design. The results show a scalable hardware design that can be used to solve small and large systems with dynamic parallelism.

BibTeX

@inproceedings{iros2017_designtimeimprov,
  title = {Design-time improvement using a functional approach to specify GraphSLAM with deterministic performance on an FPGA},
  author = {Robin Appel and Hendrik Folmer and Jan Kuper and Rinse Wester and Jan Broenink},
  booktitle = {IROS 2017},
  year = {2017}
}