NeurIPS 2025poster0 citations
VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification
Patrick Yubeaton, Andre Nakkab, Weihua Xiao, Luca Collini, Ramesh Karri, Chinmay Hegde, Siddharth Garg
Abstract
This paper introduces VeriThoughts, a novel dataset designed for reasoning-based Verilog code generation. We establish a new benchmark framework grounded in formal verification methods to evaluate the quality and correctness of generated hardware descriptions. Additionally, we present a suite of specialized small-scale models optimized specifically for Verilog generation. Our work addresses the growing need for automated hardware design tools that can produce verifiably correct implementations from high-level specifications, potentially accelerating the hardware development process while maintaining rigorous correctness guarantees.
verilogdataset generationformal verificationreasoning
BibTeX
@inproceedings{
yubeaton2025verithoughts,
title={VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification},
author={Patrick Yubeaton and Andre Nakkab and Weihua Xiao and Luca Collini and Ramesh Karri and Chinmay Hegde and Siddharth Garg},
booktitle={The Thirty-ninth Annual Conference on Neural Information Processing Systems Datasets and Benchmarks Track},
year={2025},
url={https://openreview.net/forum?id=3Z8fWHKqlu}
}