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Dimitrios Tsaras

2 accepted papers

2026

Beyond Tokens: Enhancing RTL Quality Estimation via Structural Graph Learning

ICML 2026poster

Estimating the quality of register transfer level (RTL) designs is crucial in the electronic design automation (EDA) workflow, as it enables instant feedback on key performance metrics like area and delay without the need for time-consuming logic synthesis. While recent approaches have leveraged lar…

Cited by 0SourceScholar
2025

The Graph’s Apprentice: Teaching an LLM Low-Level Knowledge for Circuit Quality Estimation

IJCAI 2025

Logic synthesis is a crucial phase in the circuit design process, responsible for transforming hardware description language (HDL) designs into optimized netlists. However, traditional logic synthesis methods are computationally intensive, restricting their iterative use in refining chip designs. Re