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Warren J. Gross

8 accepted papers

2021

High-Throughput VLSI Architecture for Soft-Decision Decoding with ORBGRAND

ICASSP 2021accepted

Guessing Random Additive Noise Decoding (GRAND) is a recently proposed approximate Maximum Likelihood (ML) decoding technique that can decode any linear error-correcting block code. Ordered Reliability Bits GRAND (ORBGRAND) is a powerful variant of GRAND, which outperforms the original GRAND techniq…

Cited by 0SourceScholar
2021

Towards Practical Near-Maximum-Likelihood Decoding of Error-Correcting Codes: An Overview

ICASSP 2021accepted

While in the past several decades the trend to go towards increasing error-correcting code lengths was predominant to get closer to the Shannon limit, applications that require short block length are developing. Therefore, decoding techniques that can achieve near-maximum-likelihood (near-ML) are ga…

Cited by 0SourceScholar
2019

Learning Recurrent Binary/Ternary Weights

ICLR 2019poster

Recurrent neural networks (RNNs) have shown excellent performance in processing sequence data. However, they are both complex and memory intensive due to their recursive nature. These limitations make RNNs difficult to embed on mobile devices requiring real-time processes with limited hardware resou…

2017

A distributed constrained-form support vector machine

ICASSP 2017accepted

Despite the importance of distributed learning, few fully distributed support vector machines exist. In this paper, not only do we provide a fully distributed nonlinear SVM; we propose the first distributed constrained-form SVM. In the fully distributed context, a dataset is distributed among networ…

Cited by 0SourceScholar
2017

Sparsely-Connected Neural Networks: Towards Efficient VLSI Implementation of Deep Neural Networks

ICLR 2017poster

Recently deep neural networks have received considerable attention due to their ability to extract and represent high-level abstractions in data sets. Deep neural networks such as fully-connected and convolutional neural networks have shown excellent performance on a wide range of recognition and cl…

Cited by 128SourceScholar
2016

Hardware implementation of FIR/IIR digital filters using integral stochastic computation

ICASSP 2016accepted

Stochastic computing (SC) has received much recent attention due to its inherent fault-tolerance and low implementation cost compared to binary radix representations. SC has been proposed for various signal processing applications such as digital filters. The prior art in stochastic FIR filters can…

Cited by 0SourceScholar
2016

Partitioned successive-cancellation list decoding of polar codes

ICASSP 2016accepted

Successive-cancellation list (SCL) decoding is an algorithm that provides very good error-correction performance for polar codes. However, its hardware implementation requires a large amount of memory, mainly to store intermediate results. In this paper, a partitioned SCL algorithm is proposed to re…

Cited by 0SourceScholar