TC: Throughput centric successive cancellation decoder hardware implementation for polar codes

Tiben Che; Jingwei Xu; Gwan S. Choi

ICASSP 2016accepted0 citations

TC: Throughput centric successive cancellation decoder hardware implementation for polar codes

Abstract

This paper presents a hardware architecture of fast simplified successive cancellation (fast-SSC) algorithm for polar codes, which significantly reduces the decoding latency and dramatically increases the throughput. Algorithmically, fast-SSC algorithm suffers from the fact that its decoder scheduling and the consequent architecture depends on the code rate; this is a challenge for rate-compatible system. However, by exploiting the homogeneousness between the decoding processes of fast constituent polar codes and regular polar codes, the presented design is compatible with any rate. The scheduling plan and the intendedly designed processing core are also described. Results show that, compared with the state-of-art decoder, our design can achieve at least 60% latency reduction for the codes with length N = 1024. By using Nangate FreePDK 45nm process, proposed design can reach throughput up to 5.81 Gbps and 2.01 Gbps for (1024,870) and (1024, 512) polar code, respectively.

BibTeX

@inproceedings{icassp2016_tcthroughputcent,
  title = {TC: Throughput centric successive cancellation decoder hardware implementation for polar codes},
  author = {Tiben Che and Jingwei Xu and Gwan S. Choi},
  booktitle = {ICASSP 2016},
  year = {2016}
}