QiMeng-VPID: Verification-Grounded Port-Level Iterative Decomposition for Complex Verilog Generation

Abstract

While Large Language Models (LLMs) have shown promise in translating natural-language specifications to Register-Transfer Level (RTL) designs, they often fail on complex, port-rich IPs. Existing frameworks typically separate generation from debugging, relying on static decomposition and iterative repair, which is hard to verify and yields unstable, inefficient maintenance. In this work, we propose VPID, a multi-agent framework for generating complex Verilog that achieves monotonic functional improvement. Given RTL’s inherent concurrency and the alignment between verification and port-level behavior, our key insight is to treat ports as verifiable boundaries for dynamic decomposition, enabling fine-grained analysis to pinpoint root causes and guide targeted debugging. Specifically, we implement a behavior locking mechanism that preserves the behavior of verified ports to ensure monotonicity, preventing regressions in correct functionalities. To accelerate convergence, we introduce an experience-guided refinement strategy that distills historical waveform mismatches into constraints, guiding the targeted debugging for the unverified ports. Together with precise Abstract Syntax Tree (AST)-based code extraction, these mechanisms enable an efficient incremental generation workflow. Experiments on RealBench demonstrate that VPID outperforms both one-pass general-purpose LLMs and existing agent-based frameworks in both syntax and functional correctness, presenting a robust approach for automating Verilog generation for complex RTL designs.