Jaeyong Chung

2 accepted papers

2026

GSRQ: Gain-Shape Residual Quantization for Sub-1-bit KV Cache

Soosung Kim, Minjae Park, Eui-Young Chung, Jaeyong Chung

ICML 2026poster

The deployment of Large Language Models (LLMs) with extended context windows is increasingly constrained by the linear growth of Key-Value (KV) cache memory. Vector Quantization (VQ) is a key enabler for pushing KV cache storage toward the sub-1-bit regime; in particular, Residual Quantization (RQ) …

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2026

Two-Stage Unit Tying for Simplifying Differentiable Logic Gate Networks

Seungheon Lee, Jeongmin Sun, Jaeyong Chung

ICML 2026poster

Differentiable logic gate networks map learned models directly to gate-level circuits, enabling ultra-low-latency inference, yet their logic footprint often exceeds FPGA capacity budgets. Tightly fitting a trained model to a target FPGA requires a post-training mechanism to trade off network complex…

Cited by 0 Source ↗Scholar ↗