2015
Accelerating and deceleratingmin-sum-based gear-shift LDPC decoders
ICASSP 2015accepted
Low-Density Parity-Check (LDPC) decoders typically implement a single decoding algorithm or update rule, which narrows down the design space of the decoder and maintains its overall simplicity. However, gear-shift techniques combine multiple decoding algorithms, update rules and quantization of the…