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Naresh R. Shanbhag

10 accepted papers

2023

Boosting the Accuracy of SRAM-Based in-Memory Architectures Via Maximum Likelihood-Based Error Compensation Method

ICASSP 2023accepted

SRAM-based analog in-memory computing (IMC) architectures have demonstrated high energy efficiency and compute density over digital accelerators for machine learning. However, their compute SNR and achievable dot product (DP) dimension are limited by the analog nature of computations. We present a M…

Cited by 0SourceScholar
2023

Enhancing the Accuracy of Resistive In-Memory Architectures using Adaptive Signal Processing

ICASSP 2023accepted

Analog in-memory computing architectures (IMCs) have exhibited high energy efficiency over conventional digital architectures. The use of resistive memory arrays such as magnetic RAM (MRAM) in IMCs has significant potential due to their high-density and non-volatility. However, the analog nature of…

Cited by 0SourceScholar
2022

IMPQ: Reduced Complexity Neural Networks Via Granular Precision Assignment

ICASSP 2022accepted

The demand for the deployment of deep neural networks (DNN) on resource-constrained Edge platforms is ever increasing. Today’s DNN accelerators support mixed-precision computations to enable reduction of computational and storage costs but require networks with precision at variable granularity, i.e…

Cited by 0SourceScholar
2020

Low-Complexity Fixed-Point Convolutional Neural Networks For Automatic Target Recognition

ICASSP 2020accepted

There has been growing interest in developing neural network based automatic target recognition systems for synthetic aperture radar applications. However, these networks are typically complex in terms of storage and computation which inhibits their deployment in the field, where such resources are…

Cited by 0SourceScholar
2018

An Analytical Method to Determine Minimum Per-Layer Precision of Deep Neural Networks

ICASSP 2018accepted

There has been growing interest in the deployment of deep learning systems onto resource-constrained platforms for fast and efficient inference. However, typical models are overwhelmingly complex, making such integration very challenging and requiring compression mechanisms such as reduced precision…

Cited by 0SourceScholar
2018

True Gradient-Based Training of Deep Binary Activated Neural Networks Via Continuous Binarization

ICASSP 2018accepted

With the ever growing popularity of deep learning, the tremendous complexity of deep neural networks is becoming problematic when one considers inference on resource constrained platforms. Binary networks have emerged as a potential solution, however, they exhibit a fundamentallimi-tation in realizi…

Cited by 0SourceScholar
2017

Minimum precision requirements for the SVM-SGD learning algorithm

ICASSP 2017accepted

It is well-known that the precision of data, weight vector, and internal representations employed in learning systems directly impacts their energy, throughput, and latency. The precision requirements for the training algorithm are also important for systems that learn on-the-fly. In this paper, we…

Cited by 0SourceScholar
2016

Analysis of error resiliency of belief propagation in computer vision

ICASSP 2016accepted

Probabilistic inference is a versatile tool to solve a large variety of pixel-labeling problems in computer vision such as stereo matching and image denoising. Belief Propagation (BP) is an effective method for such inference tasks, and has also shown attractive error-resilience properties—the abili…

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2016

Perfect error compensation via algorithmic error cancellation

ICASSP 2016accepted

This paper presents a novel statistical error compensation (SEC) technique — algorithmic error cancellation (AEC)-for designing robust and energy-efficient signal processing and machine learning kernels on scaled process technologies. AEC exhibits a perfect error compensation (PEC) property, i.e., i…

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2015

An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks

ICASSP 2015accepted

In this paper, an energy efficient, memory-intensive, and high throughput VLSI architecture is proposed for convolutional networks (C-Net) by employing compute memory (CM) [1], where computation is deeply embedded into the memory (SRAM). Behavioral models incorporating CM's circuit non-idealities an…

Cited by 0SourceScholar