2026
A Hierarchical Circuit Symbolic Discovery Framework for Efficient Logic Optimization
ICLR 2026poster
The efficiency of Logic Optimization (LO) has become one of the key bottlenecks in chip design. To prompt efficient LO, many graph-based machine learning (ML) methods, such as graph neural networks (GNNs), have been proposed to predict and prune a large number of ineffective subgraphs of the LO heur…